1. Technical Field
The present disclosure relates to a circuit architecture and a method for solving the problem of the parallel supplying during the testing steps, in particular electromagnetic wafer sort (EMWS) testing, of a plurality of electronic devices integrated on a semiconductor wafer and arranged in parallel on said wafer.
The disclosure further relates to creating connections between the various devices on the wafer, for then using them during the testing of the wafer itself to supply them, due to the non-negligible power required by the operation of the devices themselves.
The disclosure particularly, but not exclusively, relates to applications of a process of electric wafer sort (EWS) and/or electromagnetic wafer sort (EMWS) and/or wafer level burn-in (WLBI) intended for the quality control in the manufacturing of electronic devices integrated on semiconductor wafer.
2. Description of the Related Art
As it is well known in this specific technical field, an electric selection of electronic devices integrated on a semiconductor wafer (testing EWS) is carried out by electrically connecting a testing apparatus, i.e. a tester which carries out the measurements, to a wafer whereon components, devices or electronic circuits have been realized according to known processes of semiconductor monolithic integration.
To realize this connection between the testing apparatus and the wafer an interface is provided known as “probe card”. This interface is substantially an electronic board substantially constituted by a printed circuit board (PCB) and by some hundreds (sometimes thousands) of probes which electrically connect the tester to ends known as pads of the integrated electronic devices to be tested.
A known type of electric testing on wafer is WLBI (Wafer Level Burn-In) and is used to check the reliability of a device by using test conditions at particularly high activation energies (in relation to the specific device and to the technology used for realizing it) to accelerate the failure mechanisms.
One of the several known solutions of WLBI testing has been developed in Motorola and is described in an article:
Electronic Components and Technology Conference 2000-Sacrificial Metal Wafer Level Burn-In KGD-Wilburn L. Ivy Jr., Prasad Godavarti, Nouri Alizy, Teresa Mckenzie, Doug Mitchell-Motorola Incorporated.
This article takes into consideration the creation of metallic connections on the wafer which connect to each other groups of electronic devices in a clusters architecture.
These metallic connections, that could be also considered as grids, are realized outside the various devices by overlapping, at the end of the manufacturing step, strips of sacrificial metal thereon. These strips are removed and completely eliminated by means of an acid etching at the end of the WLBI testing operations, to allow to carry out an electric testing on each single electronic device.
Some studies are currently ongoing to carry out a testing of the electromagnetic type (and at the most wireless), even during the step of manufacturing the devices so as to avoid, as much as possible (and at the most to completely avoid) the use of the probes of the testing apparatus. These studies are focused towards carrying out a parallel testing onto a plurality of devices or onto a whole wafer.
In fact, although advantageous under several aspects, and substantially meeting the aim, the probes which connect the tester to the wafer have some drawbacks; for example, they can lead to a damaging of the pads of the electronic devices selected for the testing. This damaging can cause problems in the assembly of the electronic devices that have passed the quality control at the end of the testing.
Moreover, for the electric or electromagnetic selection of said plurality of electronic devices, carried out in parallel, probe cards with a very high number of probes are used. This implies an increase of the contacting problems, and thus an increase of the electric continuity problems between the probe card and the wafer, or, better, between the probes and the pads of the electronic device, with subsequent problems of loss of electric performance.
Other problems are due to the mechanical limits of last generation state-of-the-art electronic devices, which have a high number of pads to be contacted, or have pads of reduced area, or even pads which are often very close to each other.
In case it is possible, in the future, to pass from completely electric testing mode to electromagnetic (completely or in part) testing mode, the introduction in each device of reception and transmission circuits is provided, so called transceivers or transponders. This will imply an increase of area of each electronic device, even if this need is to be considered unavoidable.
By using an electromagnetic testing the number of probes of the current testing apparatuses will be reduced or even eliminated.
However, the parallel electric or electromagnetic testing of a plurality of devices arranged on a single wafer, raises the problem of how to supply them enough to operate under testing conditions.
Obviously, when the testing parallelism increases, in consequence the power that the electromagnetic testing will have to use for the simultaneous supply of the various devices will increase.
In substance, the problem of supplying the various electronic devices which are tested in parallel is tied to the fact that these devices should operate simultaneously during the testing.